org 0x0

start:
    ;MUL A, B
    mov a,#0x4
	mov b,#0x6
	MUL ab
	mov 0x20,A
	mov 0x21,B
	mov 0x22,PSW
	
	;MUL A, B
	mov A,#0x15
	mov B,#0x60
	mul ab
	mov 0x23,A
	mov 0x24,B
	mov 0x25,PSW
	
	;DIV AB
	MOV A,#0x00
	MOV PSW,A
	mov a,#0x15
	mov b,#0x00
	DIV ab
	MOV 0x26,PSW
	
	;DIV AB
	mov a,#0x15
	mov b,#0x4
	DIV ab
	mov 0x27,A
	mov 0x28,B
	mov 0x29,PSW
	
	;DIV AB
	mov a,#0x67
	mov b,#0x14
	DIV ab
	mov 0x2a,A
	mov 0x2b,B
	mov 0x2c,PSW
	
	;DA
	MOV A,#0x37
	add A,#0x36
	DA A
	MOV 0x2d,A
	
	MOV A,#0x37
	add A,#0x99
	DA A
	MOV 0x2e,A
	
	sjmp $
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw 0x20,0x18
	dw 0x21,0x00
	dw 0x22,0x00
	dw 0x23,0xe0
	dw 0x24,0x07
	dw 0x25,0x05
	dw 0x26,0x05
	dw 0x27,0x05
	dw 0x28,0x01
	dw 0x29,0x00
	dw 0x2a,0x05
	dw 0x2b,0x03
	dw 0x2c,0x00
	dw 0x2d,0x73
	dw 0x2e,0x36
	
	dw REG_SP,    0x7
	dw REG_A,     0x36
	dw REG_B,     0x03
	dw REG_PC,    0x53
	dw REG_DPTR,  0x0
	dw REG_PSW,   0xc0
	dw CYCLE,     69
	dw REG_R0,    0x0
	dw REG_R1,    0x0
	dw REG_R2,    0x0
	dw REG_R3,    0x0
	dw REG_R4,    0x0
	dw REG_R5,    0x0
	dw REG_R6,    0x0
	dw REG_R7,    0x0
	dw REG_END
end
	